(1) Field of the Invention
This invention relates to a computer system with a Peripheral component interconnect (PCI) Express interface, and more particularly to a computer system that adapts a high speed PCI Express interfaced apparatus to match a relative low speed PCI Express connector.
(2) Description of Related Art
A computer system typically includes a main board with a system bus formed thereon as a basic component. Various devices such as a central processing unit (CPU), a chip set, and memories adapted on the main board are communicated with each other. The chip set who plays a role of ruling signal and data transmission on the system bus and periphery buses is usually determined with the choice of the CPU. In addition, there should be various connectors associated with such periphery buses for connecting periphery components such as a displaying card, a hard disk, a floppy disk, a CDROM, etc.
Referring to FIG. 1, there is a prior art main board with a separated Southbridge (SB) 30 and a Northbridge (NB) 20. The NB 20 deals with data and signal transmission between a CPU 10, a main memory 24, and an accelerated graphics port (AGP) connectors 22. The NB 20 also communicates with the SB 30 by using a particular transmission protocol. The SB 30 has a PCI controller, an integrated devices electronics (IDE) controller, a universal serial bus (USB) controller, and other specific controllers for controlling various periphery components such as a PCI connector 32, a CDROM/hard disk 34, a floppy disk 36, and a keyboard/mouse 38, so as to deal with the input/output (I/O) signals from the periphery components 32,34,36,38. Furthermore, the SB 30 also transmits interrupt requests from the periphery components 32,34,36,38 to the NB 20 for asking the CPU 10 to set up a proper operation schedule dealing with the periphery components 32,34,36,38.
An AGP interface, which is developed according to the need of a huge data stream resulted in a texture mapping technique of a 3D image, is provided to overcome the limitation of transmission speed of the traditional PCI interfaced displaying card. However, other advance PCI interfaced periphery components, such as an SCSI hard disk with an ultra 320 standard or an Ethernet adapter with a supporting transmission speed up to 10 GB, can provide a transmission speed surpassing that of PCI interface and thus cannot be compatible with the traditional AGP interface anymore. As a result, a new generation of the I/O port interface, the so-called PCI Express interface, is raised.
The PCI Express interface standard, which is developed to replace the traditional PCI interface, is provided with high transmission speed and strong extension ability. For a better understanding, a typical computer system with the PCI Express interface is shown in FIG. 2. The chip set 40 of the computer system is able to connect to a PCI Express connector 41 with or without a switch 42, and connect to a PCI connector through a bridge 44. Upon such an arrangement, the developed PCI Express interface is able to support the traditional PCI interfaced apparatus and has a potential to replace the tradition PCI interface, or even the AGP interface.
The PCI Express interface features a serial-connection, point-to-point, and low-voltage-differential-signal (LVDS) (by using two transmission lines to create a voltage differential to represent logic signals 0 and 1) transmission, and has an increased transmission speed but with a reduced noise level. Under the technique standard of PCI Express interface, a basic PCI Express link specifies two pairs of LVDSs, one for transmitting signals and the other for receiving signals. Such a link is also represented as a “lane” with a standardized bit rate of about 2.5 Gbps.
As mentioned, it is known that either the bandwidth or the transmission speed of the PCI Express interface is decided by the amount of “lanes”, and the increase in the “lanes” implies an increase of contacts within the PCI Express connector. Moreover, the PCI Express connector may have a selectable lane width of ×1, ×2, ×4, ×8, ×12, ×16, or ×32 with respect to a bit rate ranged from 2.5 Gbps to 80 Gbps.
FIG. 3 shows a typical ×1 PCI Express connector 43a, and FIG. 10 shows a corresponding contact definition table. FIG. 4 shows a typical ×4 PCI Express connector 43b, and FIG. 11 shows a corresponding contact definition table. In the contact definition tables of FIGS. 10 and 11, label “RSVD” represents the preserved contacts, label “GND” represents the grounding contacts, labels “JTAG1” to “JTAG5” represent testing contacts, label “3.3Vaux” represents a contact for applying a 3.3V auxiliary power, labels “SMCLK” and “SMDAT” represent respectively system management bus clock and data which control the data transmission between the connector and the controller, labels “REFCLK+” and “REFCLK−” represent contacts for delivering reference clock signals for generating differential pairs, labels “HSOp(i)” and “HSOn(i)” represent contacts for transmitting differential pairs, labels “HSIp(i)” and “HSIn(i)” represent contacts for receiving differential pairs, and labels “PRSNT#1” and “PRSNT#2” represent contacts for detecting the presence of a hot plug.
As mentioned, the ×4 PCI Express connector 43b has more “lanes” to represent a bigger lane width by comparing to the ×1 PCI Express connector 43a, and the ×4 PCI Express connector 43b has a longer slot to allocate an increased number of contacts. For a better understanding, it is shown in FIGS. 10 and 11 that the ×1 PCI Express connector 43a has only one “lane”, whereas the ×4 PCI Express connector 43b has four “lanes”. Furthermore, except for including the same contacts as that of the ×1 PCI Express connector 43a (the contacts #1˜#18), the ×4 PCI Express connector 43b has additional fourteen contacts (the contacts #19˜#32) for providing more “lanes”. The added contacts (the contacts #19˜#32) are aligned from a rear end of the original ×1 PCI Express connector 43a, i.e. from the contact #18 of FIG. 11.
As described above, the PCI Express connector with more lanes has a longer slot to allocate the increased number of contacts. Thus, the PCI Express interfaced apparatus having more lanes should have a broader area to locate golden fingers. When a conventional PCI Express connector with a preset lane width can be used to accept a PCI Express interfaced apparatus having a lane width less than that preset lane width, it is no way for such a PCI Express connector to accept another PCI Express interfaced apparatus having a lane width larger than that preset lane width.
Basically, the lane width of a PCI Express connector provided on the main board is identical to the lane width of the PCI Express controller within the chip set, and only the PCI Express interfaced apparatus with a smaller lane width with respect to the connector can be used.
In addition, almost all the PCI Express displaying cards in the market are provided with a ×16 lane width, and the respective ×16 PCI Express controller to the PCI Express displaying card is always provided in the NB. Restricted by the size and the number of contacts, the NB supporting PCI Express interface, such as the Grantsdale of Intel, cannot support the AGP interface. Therefore, in a current system, a PCI Express displaying card and an AGP displaying card cannot be used at the same time.
Accordingly, how to enable a PCI Express interface to adopt a PCI Express interfaced apparatus with a bigger lane width under any circumstance of the chip set now becomes an important topic.